1. Field of the Invention
The invention relates to a process for fabricating CMOS devices on a single semiconductor substrate, and, more particularly, to a process for providing CMOS devices with self-aligned channel stops for both n-channel and p-channel devices as well as mutual self-alignment between the two channel stops. Advantageously, the two different type channel stops are implanted using only one mask, called herein a "complementary" mask.
2. Description of the Prior Art
CMOS (Complementary Metal Oxide Semiconductor) devices provide an inherently low power static circuit technology which has the capability of providing lower power-delay product than a comparable design-rule NMOS technology. In the VLSI era, large random logic devices (such as microprocessors) are often power-limited; that is, the total power dissipation can limit the gate count of a chip and hence limit its scale of integration and ultimate performance.
In the prior art, CMOS devices formed on a bulk substrate of a given conductivity comprise both NMOS and PMOS devices in adjacent arrangement. Where the source and drain connections of one type of device are of the same conductivity as the substrate, then a well of the opposite conductivity is generally formed in the substrate surrounding the source and drain regions, to which electrical connections are made. For devices of conductivity opposite to that of the substrate, the source and drain regions are simply implanted into the substrate and electrical connections made thereto.
Such devices are well-known in the art and perform adequately at spacings on the order of a few micrometers. However, in scaling down to submicrometer dimensions, punch-through occurs between source and drain, even at low voltages, as the distance between them decreases. Further, due to the increasing proximity of NMOS and PMOS devices, latch-up problems easily occur due to the formation of parasitic bipolar transistors.
In an attempt to overcome some of these problems, wells are also provided for the second group of devices. A similar concept is disclosed in IEDM Digest, pp. 752-755 (1980). However, due to the lack of channel stop formation in the structure, there is still a problem of leakage between N and P devices, thereby causing latch-up, as well as leakage between N and N devices and between P and P devices.